1. Technical Field
The present invention relates to electronic design automation (EDA). More specifically, the present invention relates to a method and a system for concurrently optimizing multiple routing objectives during the design of an IC chip.
2. Related Art
Advances in semiconductor technology presently make it possible to integrate large-scale systems, including hundreds of millions of transistors, onto a single semiconductor chip. This dramatic increase in semiconductor integration densities has made it considerably more challenging to efficiently perform routing in such a large-scale IC chip.
Routing an integrated circuit (IC) chip involves determining routes for metal wires which electrically connect integrated circuit devices to produce circuits that perform desired functions. Large scale IC chips are typically routed using routing software, which is typically referred to as a “routing system” or “router.”
During a routing process, router needs to optimize a routing solution based on a set of routing objectives. Conventional techniques typically optimize various optimization objectives in a serial or sequential manner. For example, a conventional technique may begin by eliminating “difficult” design rule violations (e.g., different net design rule violations). Next, the conventional technique may eliminate “easy” design rule violations (e.g., same net design rule violations). Once all design rule violations have been eliminated, the technique may then further perturb the routing solution to optimize other parameters.
Unfortunately, these optimization objectives are often inter-related, and hence a sequential optimization can increase convergence time and result in suboptimal routing solutions. For example, once a conventional technique has eliminated design rule violations, the technique may perturb the design to optimize DFM-related optimization objectives, but doing so may create new design rule violations, which will need to be fixed by performing an additional iteration of the routing optimization process. As a result, a sequential approach for optimizing the optimization objectives can increase the convergence time. Furthermore, when a conventional technique eliminates DRC violations, the technique is usually oblivious to other optimization objectives. Unfortunately, once the approach eliminates DRC violations, it may not be able to sufficiently optimize other objectives because most of the routing decisions have already been made by this stage without any consideration of the other objectives.